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<p>The configuration structure for CSI Controller.  
 <a href="struct_x_csi2_tx___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a74df52877264a60e8afae948446f7464"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___config.html#a74df52877264a60e8afae948446f7464">DeviceId</a></td></tr>
<tr class="memdesc:a74df52877264a60e8afae948446f7464"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Id.  <a href="#a74df52877264a60e8afae948446f7464">More...</a><br/></td></tr>
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<tr class="memitem:a3a98c112448388a88d774028e6621d5b"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___config.html#a3a98c112448388a88d774028e6621d5b">BaseAddr</a></td></tr>
<tr class="memdesc:a3a98c112448388a88d774028e6621d5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Base address of CSI2 Rx Controller.  <a href="#a3a98c112448388a88d774028e6621d5b">More...</a><br/></td></tr>
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<tr class="memitem:a81490985967772106c88ddf719652d37"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___config.html#a81490985967772106c88ddf719652d37">MaxLanesPresent</a></td></tr>
<tr class="memdesc:a81490985967772106c88ddf719652d37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max value of Lanes.  <a href="#a81490985967772106c88ddf719652d37">More...</a><br/></td></tr>
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<tr class="memitem:ab432923634a1d5e2b780e9602658e64c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___config.html#ab432923634a1d5e2b780e9602658e64c">ActiveLanes</a></td></tr>
<tr class="memdesc:ab432923634a1d5e2b780e9602658e64c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Lanes configured.  <a href="#ab432923634a1d5e2b780e9602658e64c">More...</a><br/></td></tr>
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<tr class="memitem:a661cd2b2d33ae733dffafdd736aaaaa2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_csi2_tx___config.html#a661cd2b2d33ae733dffafdd736aaaaa2">FEGenEnabled</a></td></tr>
<tr class="memdesc:a661cd2b2d33ae733dffafdd736aaaaa2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame End generation enabled.  <a href="#a661cd2b2d33ae733dffafdd736aaaaa2">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>The configuration structure for CSI Controller. </p>
<p>This structure passes the hardware building information to the driver </p>
</div><h2 class="groupheader">Field Documentation</h2>
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          <td class="memname">u32 XCsi2Tx_Config::ActiveLanes</td>
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<p>Number of Lanes configured. </p>
<p>Range 0 - 3 </p>

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          <td class="memname">UINTPTR XCsi2Tx_Config::BaseAddr</td>
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<p>Base address of CSI2 Rx Controller. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga79fec6c8f14f43478aedaaaae040447e">Csi2TxSelfTestExample()</a>, <a class="el" href="group__csi2tx.html#gac9ea3e1e3c6a8ecc2f5074caca2e4c6b">XCsi2Tx_CfgInitialize()</a>, <a class="el" href="group__csi2tx.html#ga874801fd63ef703d0b8ec36379b743a7">XCsi2Tx_Configure()</a>, <a class="el" href="group__csi2tx.html#ga3ff13690fd3d7cbb9ef1b0b8bf579235">XCsi2Tx_GetIntrEnable()</a>, <a class="el" href="group__csi2tx.html#ga40b9d2c4e3ac95c5a55c085ba0412304">XCsi2Tx_GetIntrStatus()</a>, <a class="el" href="group__csi2tx.html#ga7aceee43ac75b5e2e7fb5c072e99543d">XCsi2Tx_GetLineCountForVC()</a>, <a class="el" href="group__csi2tx.html#gad74fa52c21a09573d7838c8ec469cb82">XCsi2Tx_GetShortPacket()</a>, <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>, <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>, and <a class="el" href="group__csi2tx.html#ga1f42ddbe8c72819877271b1e2b1b2f66">XCsi2Tx_SetLineCountForVC()</a>.</p>

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<p>Device Id. </p>

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          <td class="memname">u32 XCsi2Tx_Config::FEGenEnabled</td>
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<p>Frame End generation enabled. </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#ga7aceee43ac75b5e2e7fb5c072e99543d">XCsi2Tx_GetLineCountForVC()</a>, <a class="el" href="group__csi2tx.html#ga60da0ba950424b0e90d2cf108eefed2c">XCsi2Tx_InterruptClear()</a>, <a class="el" href="group__csi2tx.html#gad54b9d4f661d683594d59fe7ab428962">XCsi2Tx_IntrDisable()</a>, <a class="el" href="group__csi2tx.html#ga2caa416a631b37b3414f3ebe811fb50e">XCsi2Tx_IntrEnable()</a>, <a class="el" href="group__csi2tx.html#gafc4a705bd3a295ac372fa02eb578af4d">XCsi2Tx_IntrHandler()</a>, and <a class="el" href="group__csi2tx.html#ga1f42ddbe8c72819877271b1e2b1b2f66">XCsi2Tx_SetLineCountForVC()</a>.</p>

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<p>Max value of Lanes. </p>
<p>Range 0 - 3 </p>

<p>Referenced by <a class="el" href="group__csi2tx.html#gac3002b53f14fc92a2f9dbd70466fb54f">XCsi2Tx_IsActiveLaneCountValid()</a>, and <a class="el" href="group__csi2tx.html#ga8c4f599fd297b0b87b7b5028bc59a1a4">XCsi2Tx_SelfTest()</a>.</p>

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